1. Technical Field
The present disclosure relates to circuits and methods for driving flat panel displays and, more particularly, to source driving circuits and methods, and a liquid crystal display apparatus capable of reducing power consumption for driving data lines of flat panel displays.
2. Discussion of Related Art
Various types of flat panel displays, such as a liquid crystal display (LCD), a plasma display panel (PDP), an electroluminescence display panel, and the like, have been developed to replace traditional cathode ray tube (CRT) displays. Such flat panel displays are suitable for devices and applications requiring small dimensions, light weight, and low power consumption. For example, LCDs can be operated using large-scale integration (LSI) drivers, because LCDs can be driven by a low-voltage power supply and have a low power consumption. Accordingly, LCDs have been widely implemented for laptop computers, cellular phones, pocket computers, automobiles, and color televisions. For features such as light weight, smaller dimensions, and low power consumption, LCD devices are widely used in portable devices.
FIG. 1 is a diagram illustrating a conventional display system.
Referring to FIG. 1, the display system 100 includes a display panel 110 (for example, LCD) and a plurality of components for driving/controlling the display panel 110 including a source driving IC 120, a gate driving IC 130, a controller 140 having a graphic random access memory (GRAM), and a power generator 150. The controller 140 generates control signals for controlling the power generator 150, the source driving IC 120 and the gate driving IC 130.
The display panel 110 includes a plurality of data lines D1 to Dm that are connected to the source driving IC 120 and a plurality of gate lines G1 to Gn that are connected to the gate driving IC 130. The display panel 110 includes a plurality of pixels/subpixels that are arrayed in a matrix of rows and columns. The pixels/subpixels in a given column are commonly connected to a data line. Assuming the display panel 110 is a TFT-LCD, the display panel 110 may include a thin-film transistor (TFT) board including a plurality of pixel/subpixel units arranged in matrix form. As illustrated in FIG. 1, each pixel/subpixel unit includes a TFT, a liquid crystal capacitor CL, which is connected between a drain electrode of the TFT and a common electrode VCOM, and a thin-film storage capacitor Cst, which is connected in parallel with the liquid crystal capacitor CL. The storage capacitor Cst stores an electric charge so that an image on the display is maintained during a non-selected period. The liquid crystal capacitor CL is formed by a common electrode VCOM of a color filter plate, a pixel electrode of the TFT, and liquid crystal material therebetween. A source electrode of the TFT is connected to a data line and a gate electrode of the TFT is connected to a gate line. The TFT acts as a switch that applies a source voltage on the data line to the pixel electrode when a gate driver signal on the gate line is applied to the gate of the TFT.
The power generator 150 generates a plurality of reference voltages, including, AVDD (source driver power supply), and GVDD (gamma reference voltage), which are applied to the source driving IC 120, VCOMH (high common electrode voltage) and VCOML (low common electrode voltage), which are applied to the common voltage electrode VCOM of the display panel 110, and VGON (gate driver turn-on voltage) and VGOFF (gate driver turn-off voltage), which are applied to the gate driver 1C 130 for driving selected gate lines.
The controller 140 receives as input a plurality of driving data signals and driving control signals (not shown) that are output from an image supply source for example, a main board of a computer (not shown). The driving data signals includes R, G, and B data for forming an image on the display panel 110. The driving control signals include vertical synchronous signals, horizontal synchronous signals, a data enable signal, and a clock signal. The controller 140 outputs to the source driving IC 120 a plurality of display data signals DDATA, which correspond to R, G, and B data, and source control signals. The controller 140 outputs gate control signals for controlling the gate driving IC 130. The controller 140 controls the timing for which data and control signals are output from the source driving IC 120 and gate driving IC 130. For example, in one mode of operation, the controller 140 generates the source and gate control signals such that the gate driving IC 130 transmits a gate driver output signal to each gate line G1 to Gn in a consecutive manner and data voltage is selectively applied to each pixel/subpixel in an activated row, one by one, in order. In another mode of operation, the pixels/subpixels can be charged by sequentially scanning pixels/subpixels in a first column and, thereafter, scanning pixels/subpixels in a next column.
The gate driving IC 130 includes a plurality of gate drivers (not shown) that drive gate lines G1 to Gn, respectively. The source driving IC 120 includes a plurality of source driver circuits 120a to 120m that drive data lines D1 to Dm, respectively.
FIG. 2 is a schematic diagram illustrating a conventional source driving circuit 200 in the system 100 of FIG. 1.
In general, as illustrated in FIG. 2, the source driving circuit 200 includes a source driver circuit 120i that drives a corresponding data line Di, and a grayscale voltage generator 230. The source driving circuit 200 of FIG. 2 illustrates a conventional architecture of the source driver IC 120 of FIG. 1 where there is one source driver circuit 120i for each data line (or RGB channel). The grayscale generator 230 may be included in the power generation circuit 150 of FIG. 1. The output of the gray scale generator 230 is commonly coupled to each source driver circuit 120_1 to 120—m of the source driving IC 120 in FIG. 1.
In general, the source driver circuit 120i includes a polarity inversion circuit 210, a latch circuit 220, a gamma decoder 240, and a driving buffer 250. The source driver 120i is controlled by a plurality of control signals that include a polarity control signal M, a latch control signal S_LATCH, and switching control signals. In addition, the source driver 120i receives as inputs grayscale reference voltages that are generated by the grayscale voltage generator 230.
The source driver circuit 120i receives input display data DDATA of an n-bits for R, G, or B data from the GRAM controller 140. The polarity inversion circuit 210 receives the display data DDATA and controls a polarity of the display data DDATA in response to the polarity control signal M. For example, when the polarity control signal M is logic “0”, the polarity of the display data DDATA remains the same as the original display data (positive polarity). On the other hand, when the polarity control signal M is logic “1”, the polarity of the display data DDATA is reversed to be inverted display data (negative polarity).
The latch circuit 220 latches the n-bit display data output from the polarity inversion circuit 210 in response to the latch control signal S_LATCH. The latch circuit 220 outputs the latched display data to the gamma decoder 240. The grayscale voltage generator 230 generates and outputs 2″ different grayscale voltages to the gamma decoder 240. The gamma decoder 240 decodes the n-bit display data output from the latch circuit 220, and selects and outputs a grayscale voltage to the driving buffer 250.
The driving buffer 250 buffers and amplifies the grayscale voltage output from the gamma decoder 240. The amplified grayscale voltage is selectively applied to the data line of the display panel 110 in response to the switching control signal.
An equivalent capacitance Ceq is present in the source driving signal Sm connected to the common voltage VCOM.
FIG. 3 is a diagram illustrating a conventional common voltage driver circuit 300, which may be included in the power generator 150 of FIG. 1, for driving the common electrode VCOM of the display panel 110.
Referring to FIG. 3, the common voltage driver circuit 300 includes first and second drivers 310 and 320, switches 330 and 340 and capacitors 350 and 360. The first driver 310 buffers and outputs VCOMH (high common voltage) fed thereto. The capacitor 350 is connected to the output of the first driver 310 for stabilizing the output voltage. The switch 330 is controlled by a control signal VCMH_ON for selectively connecting the output of the first driver 310 to the VCOM node N and thereby driving VCOM to VCOMH. The second driver 320 buffers and outputs VCOML (low common voltage) fed thereto. The capacitor 360 is connected to the output of the second driver 320 for stabilizing the output voltage. The switch 340 is controlled by control signal VCML_ON for selectively connecting the output of the second driver 320 to the VCOM node N and thereby driving VCOM to VCOML.
FIG. 4 is a timing diagram illustrating a source driving voltage Sm driven by the source driving circuit 200 of FIG. 2 and a common electrode voltage VCOM driven by the common voltage driver circuit 300 of FIG. 3.
In FIG. 4, a white pattern of a normal black panel is illustrated as an example of the worst case pattern in the display panel 110 of FIG. 1. Referring to FIG. 4, at time T1, the polarity control signal M and the control signal VCMH_ON are enabled and the control signal VCML_ON is disabled. As a result, the switch 330 is closed and the switch 340 is opened, so that common voltage VCOM is driven to VCOMH from VCOML by the first driver 310. At this time, the source output voltage Sm is changed to VL from VH contrary to VCOM. In this exemplary embodiment, VH is the highest gray scale voltage and VL is the lowest gray scale voltage, and T is a toggling period of VCOM.
When display systems such as LCD panels are implemented in small hand-held, portable devices, it is important to reduce the power consumption needed to drive such displays, so as to preserve battery power. In general, the primary sources of power consumption when driving flat panel devices include source drivers and VCOM drivers. More particularly, with source drivers, the voltages for driving the data lines are typically designed with relatively high levels in order to enhance the driving speed of the display, for example, quickly charge and discharge the liquid crystal capacitor CL. Power consumption of the display, however, is increased in proportion to the voltage increase of the driving voltage. Further, driving the common electrode, which faces the pixel electrodes is a significant source of power consumption because the polarity of the common voltage is reversed every cycle.
Generally, the source driving voltage and the VCOM driving voltage are internal voltages that are generated by voltage generators in which such driving voltages are generated by boosting voltage/power output from an intermediate reference voltage source. Thus, the conventional source and VCOM driver circuits increase power consumption, because they use boosted voltages for driving the data lines and providing VCOM.
The average load current consumption for VCOMH driven from the supply voltage AVDD is formulated by the following Equation 1.IVCOMH=(m(VCOMH−VCOML+VH−VL)Ceq)/2T,  [Equation 1]where m denotes a number of source channels, Ceq denotes an equivalent capacitance, and T denotes a toggling period of VCOM.
In addition, the average load current consumption for VCOML driven from VL is formulated by the following Equation 2.IVCOML=(m(VCOMH−VCOML+VH−VL)Ceq)/2T  [Equation 2]
Further, the average load current consumption for source driven from voltage AVDD is formulated by the following Equation 3.ISRC=(m(VCOMH−VCOML+VH−VL)Ceq)/2T  [Equation 3]When AVDD corresponds to an output voltage boosted by an amount a provided from an external input power supply voltage, and VCL corresponds to an output voltage boosted by an amount −b provided from the external input power supply voltage, the total average current consumption is formulated by the following Equation 4.ITOT=(2a+b)*(m(VCOMH−VCOML+VH−VL)Ceq)/2T  [Equation 4]